The present invention relates to storing and playing digital audio recordings, which are collections of digital audio sample points (or samples), and in particular to looping techniques, use of cache memory and interfacing with a sample memory over a system bus.
Audio boards have been developed for computer systems which can simultaneously handle multiple channels of audio. The multiple channels may correspond to different instruments in a band, voice, etc. For any particular audio recording, multiple versions could be stored at different pitches or keys. In order to minimize the memory requirements, instead of storing all the various pitches, a single audio recording can be stored, and shifted upon playback to produce the desired pitch. This shifting is done by interpolating between an audio sample and at least a previous or next audio sample to produce the shifted audio output sample.
A technique which has been implemented in audio boards to speed up processing is the use of a cache memory. Unlike a standard cache memory used with a microprocessor for general processing, an audio sample cache memory requires more predictability regarding the data that will be needed. With multiple audio channels, there is a trade-off between the size of the cache memory and having sufficient data so that any channel doesn't run out of audio data during a realtime playback.
One technique which will occur in music generation is "looping", in which the same portion of an audio recording is repeated. The occurrence of looping can cause a discontinuity in the data required for a cache memory, since instead of sequential fetching, a jump is required. A number of techniques have been developed in the past to handle this. In one technique, two portions of the cache are used, one for the data at the start of the loop, and another for current data. Thus, the loop start data is always available. In other methods, data from outside the loop boundaries is fetched. In addition, the loop may be required to have identical levels at the start and end of the loop to avoid discontinuities, or the end of the loop could be reproduced in the start loop portion of the cache. Clearly, such techniques have disadvantages such as requiring a much larger cache memory, particularly for a large number of channels, or requiring modification of the playback data for a large number of possible sounds to be played.
The use of an audio memory on an audio board can make the audio board expensive, and can duplicate memory which will already be in a computer system in its main memory. Thus, it is desirable to have an audio board be able to share the main memory of the computer system, rather than having its own dedicated memory. However, in order to maintain realtime audio playback capability over multiple channels, the bandwidth of the system bus becomes a concern. The storing of more data than necessary in the cache requires that the data be accessed at some point over the system bus, increasing the bus bandwidth demands, and potentially slowing performance.
Additionally, a typical system bus will have a fixed minimum block size which may not match the data block size required for audio. For example, the PCI bus transfers data in doublewords, which consist of 4 bytes. However, some audio data is specified with byte level addresses, and thus, in any particular doubleword addressed in main memory, the audio recording may start at the first byte, second, third, or fourth. Thus, one, two, or three of the bytes transferred might be unnecessary for the desired audio recording. Typical cache memory systems in a microprocessor treat this as a necessary evil, and will transfer a line into the cache, which may include a large number of data not required, but is done to minimize the number of transfers over the bus and the overhead required with such a transfer.
In U.S. Pat. Nos. 5,111,727 and 5,342,990, the techniques for utilizing a cache memory in multichannel interpolative digital audio playback are disclosed. Note that there are several arbitrary design variables, in particular the interpolation order N and the number of channels L.
If the mechanism of looping is examined closely with respect to these disclosures, it will be apparent that when a loop occurs, the contents of the cache may vary depending on the history of the value of the phase increment. In particular, it can be seen that if the phase increment is smaller than unity, then when the current address exceeds the loop end address, it will do so by less than one memory location. In this case, the loop will occur immediately. However, if the phase increment exceeds one, then when the current address first exceeds the loop end address, it may do so by less or more than one memory location depending on the exact history of the value of the current address and the phase increment. If the cache is being filled with data fetched from main waveform memory at a location based on the current address at the time the memory fetch occurred, this means that the location from which data in the cache near the loop point has been fetched may come from waveform memory just below the loop end address or from just below the loop start address. This places a restriction, albeit a minor one, on the audio data. The data near the start of the loop and near the end of the loop must be identical (or virtually identical) for there to be no audio consequence of this variation in fetch location. Because the loop is expected to be audibly smooth, this identity is a desirable situation in any event, and causes few difficulties.
However, a more serious consequence of this situation is the fact that the data in the cache is not guaranteed to be fetched from the set of data points within the loop. Consider the case when the current address has just jumped back to the start of the loop. In this case, using the techniques described in '990, if a cache service request occurs at this time, data will be placed in the cache starting from the current address, and descending in address. Should the cache size be large, the data would be fetched from locations below the loop start address.
This is not a problem in general for music synthesis, but it presents problems if the data in the main waveform memory is continually being updated. In this case, it is desirable to cause the current address to loop, but continuous audio data is written into the memory defined by the loop. It can easily be seen that if the mechanism described in the '990 patent is used, then some number of audio words will need to be written both just below the end of the loop and below the start point. This inconvenience is eliminated by the current invention.